A Low-Power VLSI Neural Processor Design for High-speed Image Data Compression in a SO1 CMOS Technology

This paper presents a low-power VLSI neural processor that has been developed for highspeed vision processing based upon the frequency-sensitive self-organization (FSO) neural algorithm. Performance of this self-organization neural algorithm is proved to be efficient for adaptive vector quantization and can achieve near-optimal results. A system-on-chip design of the whole FSO neural system is described. Analysis of non-idea semiconductor effects on the FSO neural system chip design is presented. The prototyping chip for a 5 12-member competitive processor, which is a key functional unit of the FSO neural system, has been designed and fabricated in a 0.25-micron SO1 CMOS technology via the MIT Lincoln Lab. It occupies a silicon area of 1 .O mm x 1 .O mm. It operates at 50 MHz and consumes about 10 mW. The competitive processor provides a computing capability as high as 25 giga-operations per second.